In the implementation of computer circuitry, a standard method for storing microinstructions is having them reside in a read only memory (ROM). The advantage of this is that the small area of space taken by the ROM chip is most desirable but it involves the disadvantage that this ROM memory is not reprogrammable.
Another useful technique that has been used to store microinstructions is the use of a Static RAM, however, this type of memory consumes five to six times more spatial area on the printed circuit board, but it does have the advantage of permitting reprogrammability. Additionally, most Static RAM's have not been built on integrated circuit chips while, on the other hand, the ROM memory units have been manufactured on integrated chips and provide a ready availability of memory for placement on a printed circuit board.
Thus, while a computer mainframe will often require a considerable amount of control store memory circuits, these have generally been implemented as "off-chip" arrangements rather than on integrated circuit chips for ready applicability to a printed circuit board. However, many of the new computer systems dictate that there be used "on-chip" control stores, but at the same time there is no desire to give up the capability to reprogram the control store and to add new instructions, in future, to the control store. Additionally, it is desired to run microdiagnostic codes in a maintenance mode.
Generally in these cases, it is highly unlikely that the complete series of microcodes in the memory (ROM) would have to be updated, but, however, it is quite possible that several locations, or a particular given location of microcodes in the control store would be possible candidates for future updates and changes.
The resolution of this type of situation has led to the design of an architecture as described in this disclosure which provides an improvement in the design and manufacture of control stores using read only memories for holding microinstructions. This is done by using a ROM control store which consumes a small amount of integrated circuit chip space and combining it with a content addressable memory structure (CAM) whereby a miniaturized or small version of a Static RAM can be combined with read only memory and used to supplant those locations in the read only memory (ROM) which it is desired to update or change, without any degradation in performance.